1. Field of the Invention
The present invention relates to methods of estimating the delay times associated with integrated circuit logic cells and, in particular, to methods of emulating the delay time associated with individual cells and interconnected arrays of cells, such as those in ASIC (application specific integrated circuit) arrays, including cell libraries.
2. Description of Related Art
To our knowledge, in the prior art typically the delay times of integrated circuit logical cells are estimated or emulated by multiplying the total capacitive load at the output pin(s) of a given cell and a coefficient associated with the operating characteristics specific to that type of cell. However, the resulting product is a relatively rough estimate of the actual delay time. Furthermore, the time delay errors associated with individual cells are cumulative. That is, the error associated with the estimated time delay through an interconnected array of logical cells is the sum of the emulation errors associated with the individual logic cells.